This invention relates, in general, to high-voltage bipolar transistor structures, and more particularly to a high-voltage (HV) Horizontal Current Bipolar Transistor which uses the floating field regions for the improvement of breakdown voltages.
HV transistors are very useful components in applications where higher power or higher voltage swings are required. In general, the addition of HV transistors extends the range of applications for the technology. In high-voltage bipolar transistors, the open-base also known as the collector-emitter breakdown voltage (BVCEO) presents a more stringent constraint since it is usually 2 to 3 times lower than the open-emitter breakdown voltage (BVCBO). The usual approach to obtain the higher breakdown voltages in bipolar transistors is to use lower collector doping concentration in order to reduce the electric field at the base-collector junction. In that case the critical electric field for junction avalanche is achieved for higher voltages applied at the collector terminal. The mainstream bipolar technologies are based on vertical bipolar transistor structures. If the HV vertical bipolar transistors are fabricated together with high-speed (HS) transistors, additional lithography masks and ion implantation steps are required for fabrication of HV and HS collector regions, which increases the cost of the technology. The other approach to obtain the higher BVCEO is to use some form of reduced-surface-field (RESURF) effect (see Table 1, items [1]-[3]) in order to shape the potential distribution and the electric field in the base-collector depletion region. This approach is particularly suitable for lateral bipolar transistors (LBTs) since their geometry can be easily manipulated by the lithography mask design.
The Horizontal Current Bipolar Transistor (HCBT) technology is demonstrated in U.S. Pat. No. 7,038,249 (see Table 1, item [4]). HCBT has a lateral arrangement of the intrinsic transistor, in the same way as LBTs. However, the intrinsic transistor is processed on the sidewall of the silicon pillar or hill, obtained by etching, making it possible to have the optimized doping profiles in the intrinsic transistor. HCBT electrical characteristics are comparable to the characteristics of vertical bipolar transistors, with a considerable improvement over the LBTs, as has been reported in the literature (see Table 1, item [5]).
HCBT is integrated with standard 180 nm CMOS in a very simple process flow resulting in a low cost BiCMOS technology (see Table 1, item [6]). High voltage HCBTs are added to the technology at zero-cost (see Table 1, items [7], [8]). Higher BVCEO is obtained by the collector charge sharing and by the shaping of the electric field in the base-collector depletion region. In a double-emitter (DE) HCBT reported in (see Table 1, item [7]), the geometry manipulation by the lithography mask design is used to obtain a fully depleted collector and to create a drift region which shields the intrinsic base-collector junction. In this way peak electric fields at the extrinsic base-collector junction and at the end of the drift region are responsible for the transistor breakdown. BVCEO is increased from 3.4 V in case of standard high-speed single-emitter (SE) HCBT to 12.6 V in case of DE HCBT.
In this invention we report the usage of floating field regions to limit the electric field at the base-collector junction and at the end of the drift region, which further improves the breakdown voltages of HCBT structures. Floating field rings are used for junction termination of power semiconductor devices (see Table 1, item [9]). Here we use term floating field regions because they are not fabricated to encircle the device in form of a ring. They are fabricated in form of the stripes which form planar pn junctions. This approach can be applied to DE HCBT whose cross-sections are shown in FIGS. 1A and 1B, but also to single-emitter HS HCBT whose cross-section is shown in FIG. 2. In the case of SE HCBT, the lower collector doping concentration compared to DE HCBT is used. This approach is suitable for integration with CMOS since no additional processing is needed for fabrication of proposed devices.